1. Field of the Invention
The present invention relates to a semiconductor device and particularly to a semiconductor device in which a plurality of bonding pads for receiving an identical external signal are provided on a semiconductor chip.
2. Description of the Prior Art
As a package for assembling therein a semiconductor device formed on a semiconductor chip, there are known various types such as a ceramic package, a plastic package, a dual in-line package (DIP), a small out-line package (SOP) and a zigzag in-line package (ZIP). In a conventional semiconductor device, a plurality of bonding pads for receiving an identical external signal are provided on a semiconductor chip so that the semiconductor chip on which the semiconductor device is formed can be assembled in any suitable one of such different packages according to the application for which it is used. Thus, even if an arrangement of pins for externals signal is changed dependent on the package, the semiconductor chip can be assembled in a different package without changing the layout of the semiconductor device.
FIG. 1 is a schematic plan view showing a structure of a conventional semiconductor device comprising two bonding pads for receiving an identical external signal, one for a ceramic package and the other for a plastic package. Referring to FIG. 1, a device in which an integrated circuit for a dynamic random access memory (RAM) or the like is incorporated is formed on a semiconductor chip 1. A first bonding pad 3a for receiving a signal A0, a bonding pad 3b for a signal A2, and a bonding pad 3c for a signal Al are provided spaced from one another on a peripheral surface of a shorter side of the semiconductor chip 1. A second bonding pad 3d for the signal A0 is provided on a peripheral surface of a longer side of the semiconductor chip 1. An internal buffer circuit 8 for waveform-shaping or the like of the received signals is provided on the peripheral surface of the shorter side of the semiconductor chip 1. The first bonding pad 3a for the signal A0 and the second bonding pad 3d for the signal A0 are connected with each other by a wire 7. The wire 7 is connected to the internal buffer circuit 8 by a wire 7'. Thus, the first bonding pad 3a for the signal A0 and the second bonding pad 3d for the signal A0 are both connected to the internal buffer circuit 8.
FIG. 2 is a partial plan view schematically showing a structure in which the semiconductor device shown in FIG. 1 is assembled in a ceramic package. In FIG. 2, the semiconductor chip 1 is assembled in the ceramic package 2. A terminal 4a for the signal A0, a terminal 4b for the signal A2, a terminal 4c for the signal Al etc. corresponding to the first bonding pad 3a for the signal A0, the bonding pad 3b for the signal A2, the bonding pad 3c for the signal Al etc. on the semiconductor chip 1 are provided with spacings on a peripheral surface of the ceramic package 2. The first bonding pad 3a for the signal A0 and the terminal 4a for the signal A0 are bonded through a bonding wire 6a. The bonding pad 3b for the signal A2 and the terminal 4b for the signal A2 are bonded through a bonding wire 6b. The bonding pad 3c for the signal Al and the terminal 4c for the signal Al are bonded through a bonding wire 6c. In the above described structure, the first bonding pad 3a is used as a bonding pad for the signal A0, while the second bonding pad 3d for the signal A0 is not bonded. The terminal 4a for the signal A0, the terminal 4b for the signal A2, and the terminal 4c for the signal Al are connected to a fifth pin, a sixth pin, and a seventh pin (not shown), respectively, for input of external signals, which are exposed on an external surface of the ceramic package 2. The reference numerals .circle.5 , .circle.6 , and .circle.7 in the figure represent the pin numbers in the ceramic package 2. The fifth pin, the sixth pin, and the seventh pin receive the external signals A0, A2, and Al, respectively.
FIG. 3 is a partial plan view schematically showing a structure in which the semiconductor device shown in FIG. 1 is assembled in a plastic mold package. In FIG. 3, the semiconductor chip 1 is assembled in the plastic mold package 20. A terminal 5a for the signal A0, a terminal 5b for the signal A2, a terminal 5c for the signal Al etc. are provided spaced from one another on the plastic mold package 20 in a manner in which the terminals 5a, 5b, 5c etc. surround the semiconductor chip 1. The second bonding pad 3d for the signal A0 and the terminal 5a for the signal A0 are bonded by a bonding wire 6a. The bonding pad 3b for the signal A2 and the terminal 5b for the signal A2 are bonded by a bonding wire 6b. The bonding pad 3c for the signal Al and the terminal 5c for the signal Al are bonded by a bonding wire 6c. In this structure, the second bonding pad 3d is used as a bonding pad for the signal A0, while the first bonding pad 3a for the signal A0 is not bonded. The terminal 5a for the signal A0, the terminal 5b for the signal A2 and the terminal 5c for the signal Al are connected to the fifth pin, the sixth pin and the seventh pin (not shown), respectively, for receiving external signals, which are exposed on an external surface of the plastic mold package 20. The reference numerals .circle.5 , .circle.6 and .circle.7 in FIG. 3 represent the pin numbers in the plastic mold package 20. The fifth pin, the sixth pin and the seventh pin receive the external signals A0, A2 and Al, respectively.
As described above, either of the two bonding pads for the same external signal formed on the same semiconductor chip is used according to the type of a package in which the semiconductor device is assembled. Thus, bonding between the bonding pads of the semiconductor chip and the terminals of the package is simplified.
However, in the conventional semiconductor device, two bonding pads are always connected for the same external signal A0. In this case, there is involved a problem that and input capacitance viewed from the corresponding pin for receiving the external signal is increased to exceed a permissible value, causing erroneous operation.
Prior art documents related to the present invention are, for example, "A 1Mb DRAM with a Folded Capacitor Cell Structure" by F. Horiguchi et al., 1985 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 244-245 and p. 355, and "A 50 .mu.A Stand by IMW .times.1b/256KW.times.4b CMOS DRAM" by S. Fujii et al., 1986 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 266-267.
The first document discloses a structure in which switching between fast-access functions of a dynamic RAM, namely, a page mode and a nibble mode is effected by using a bonding pad method.
The second document discloses a technique in which switching between 1 MW.times.1 bit configuration and 256KW.times.4 bit configuration is effected by using a bonding pad method.